1. Field of Invention
The present invention relates to an electrostatic discharge protection circuit, and in particular, to an electrostatic discharge protection circuit provided in integrated circuits (ICs) for electrostatic discharge protection
2. Description of Related Art
In integrated circuits (IC), a plurality of devices are formed of metal oxide semiconductor (being referred to as MOS, hereinafter). However, gate oxides of such MOS devices are likely to be punched through by an abrupt high voltage caused by electrostatic discharge (being referred to as ESD, hereinafter), and a failure may be caused due to such punch-through. Therefore, it is necessary to set up in the IC an ESD protection circuit for protecting the whole IC from being damaged by external ESD.
In general, the ESD circuit eliminates electrostatic electricity by driving electrostatic electricity out of the IC in order to protect the IC from being damaged by electrostatic electricity. In other words, if an ESD event occurs, the ESD protection circuit can protect the IC from damage caused by the ESD event by means of discharging the electrostatic electricity through a path of a supply voltage VDD or VSS. However, as the microminiaturization of semiconductor process is improved, the thickness of the gate oxide of the MOS transistor is further reduced. Also, the prior art ESD protection circuits cannot protect the metal oxides of MOS transistors having reduced thickness from a high voltage environment. In such circumstances, lifetimes of MOS transistor are adversely reduced.